`timescale 1ns / 1ps
module TOP(
    input wire clk,
    input wire rst_n,
    output wire [3:0]led
);
LED_ILA u_LED_ILA(  //例化设计的模块
  .clk    (clk),
  .rst_n  (rst_n),
  .led    (led)
);


`ifdef ILA_DEBUG
    ila_0 u_ila_0(      //例化ILA IP核
      .clk     (sys_clk),
      .probe0  (sys_rst_n),
      .probe1  (pl_led)
    );
`endif

endmodule